Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof, using a control gate to program, erase and read the memory cell.
Two major issues are often implicated as memory cell dimensions are scaled down. First, the resistance in the source line increases with smaller memory cell dimensions, and a higher resistance suppresses the desirable cell current during a read event. Second, smaller memory cell dimensions result in a lower punch-through voltage VPT between the source and the bitline junction, which limits the achievable maximum floating-gate voltage Vfg during a program event. Floating-gate voltage Vfg is achieved through voltage coupling from the source region through the coupling oxide layer that is between the source and the floating gate. In a source-side injection mechanism, a higher Vfg (and thus a higher punch-through voltage VPT) is essential for a sufficient hot carrier injection efficiency.